1. Field of the Invention
The present invention relates to a signal processing apparatus for detecting a defective pixel included in a light-receiving pixel area and an optical black area of an imaging device to correct the detected defective pixel.
2. Description of the Related Art
FIG. 8 is a block diagram showing the configuration of a conventional imaging device. The imaging device shown in FIG. 8 includes an analog processing circuit 4, a clamp pulse generation circuit 68, an A/D conversion circuit 16 and a digital processing circuit 17.
As shown in FIG. 9, in a CCD solid-state imaging device, a plurality of light-receiving pixels are arranged in a matrix to form a light-receiving pixel area 2i, in which information electric charges to be generated according to incident light are stored in each light-receiving pixel. An optical black area 2b shielding light by means of an aluminum material or the like is set at the peripheral portion of the light-receiving pixel area 2i. Also in the optical black area 2b, storage pixels (hereinafter referred to as black pixels) are arranged similarly in the light-receiving pixel area 2i. In such a CCD solid state imaging device, information electric charges stored in the black pixels are transferred together with the information electric charges stored in the light-receiving pixels. Consequently, as shown in FIG. 10, black reference values B(t) from the black pixels are included in parts of a horizontal scanning period or a vertical scanning period of an output signal Y(t) from the CCD solid state imaging device.
The analog processing circuit 4 is composed of a clamp circuit 6, a CDS circuit 12 and an AGC circuit 14. The analog processing circuit 4 performs analog signal processing of the CCD output signal Y(t). The clamp circuit 6 clamps a black reference value B(t) included in the CCD output signal Y(t) in response to a clamp pulse CLP output from the clamp pulse generation circuit 68, and fixes the electric potential of all of the black levels of the CCD output signal Y(t). The clamp circuit 6 analogously averages the input black reference value B(t) for a raised period of the clamp pulse CLP while clamping the black reference value B(t). The CDS circuit 12 samples the feedthrough level and the signal level of a signal output from the clamp circuit 6 to output a signal obtained by subtracting the feedthrough level from the signal level. The AGC circuit 14 integrates a signal output from the CDS circuit 12 per period of a screen or per vertical scanning period, and generates an image signal Y(t1) the gain of which is adjusted in order that the integrated value may fall into a predetermined range.
The clamp pulse generation circuit 68 generates the clamp pulse CLP on the basis of a horizontal synchronizing signal HD and a reference clock CK, and outputs the generated clamp pulse CLP to the clamp circuit 6. The clamp pulse generation circuit 68 raises the clamp pulse CLP in a predetermined period at the beginning of a horizontal scanning period 1H, and thereby sets a clamp period in order to clamp the black reference value B(t) appearing at the head of the CCD output signal Y(t) for one line.
The A/D conversion circuit 16 quantizes the image signal Y(t1) output from the analog processing circuit 4 per one pixel to generate first image data Y(n1), and quantizes the black reference value B(t) clamped by the clamp circuit 6 to generate black data B(n). The A/D conversion circuit 16 then subtracts the black data B(n) from the first image data Y(n1) to generate second image data Y(n2). The value of the second image data Y(n2) is a value to be actually displayed after being reproduced.
The digital processing circuit 17 performs digital signal processing such as color separation and a matrix operation of the second image data Y(n2) output from the A/D conversion circuit 16 to generate third image data Y(n3) including a luminance signal and a color difference signal. Moreover, the digital processing circuit 17 performs exposure control for controlling the exposure state of the CCD solid state imaging device, and white balance control for controlling the white balance of the CCD output signal Y(t).
In the configuration described above, there is a case where a defective pixel exists in each area of the light-receiving pixel area and the optical black area. The defective pixel is produced owing to a scratch formed in a manufacturing process of the CCD solid state device, deterioration to be generated as time elapses, or the like.
For example, when the defective pixel exists in the optical black area, a black reference value having a remarkably high voltage level is included in the black reference values to be output when the black reference values obtained from the optical black area have a positive polarity. In this case, the voltage level of the black reference value after clamping is raised and the value of black data B(t) becomes large. As a result, the value of the second image data Y(n2) becomes smaller than an actual signal level. Such a failure is generated over the image data for one line in the case where the clamp processing is performed once for one line. As a result, when a reproduction image for a screen is displayed, the image becomes a crosscut image in which only some lines are seen to be relatively darker.
On the other hand, a defective pixel exists in the light-receiving area, a defective image signal is always output from the same light-receiving pixel, and fixed pattern noise is consequently generated in a reproduction image. Such noise remarkably decreases the visibility of a subject image, and emphasizes the noisy feeling of the whole screen as a result. As means for solving the problem of such a defective pixel, there is a method for reducing the noisy feeling by performing a filtering processing of blurring the whole screen. However, because the filtering processing is evenly applied to pixels other than the defective pixel in this method, the method has a problem of deteriorating the resolution of the screen.